Power Converter & Inverter Design

---

From topology selection to production validation, we design high-efficiency, production-grade power conversion systems and custom VFDs.

At MarSum Solutions, we engineer power converter and inverter systems to meet the tight automotive, industrial, HVAC/R, aerospace, and energy performance requirements. From wide-bandgap switching devices to advanced modulation techniques, our designs prioritize efficiency, EMI compliance, thermal performance, and scalability.

Our designs transition cleanly from proto bench to volume manufacturing — tuned for real-world fault conditions, input variability, and long-term reliability.

Every design begins with selecting the right topology for the constraints: power level, form factor, efficiency targets, cost, and EMI signature.

We’ve designed and optimized:

• DC–DC converters: buck, boost, buck-boost, interleaved, flyback, forward, phase-shifted full bridge (PSFB), and Ćuk (Cuk) converters
• AC–DC converters: Vienna rectifiers, 3-phase bridgeless PFC, phase-controlled thyristor (SCR) bridges
• DC–AC inverters: 2-level, 3-level NPC, Active Neutral-Point-Clamped (ANPC), asymmetric half-bridge, interleaved, and matrix (direct AC–AC) inverters for low-latency applications
• Custom topologies: resonant LLC, quasi-resonant flyback (QRC), and other topologies enabling zero-voltage (ZVS) or zero-current (ZCS) switching
   

Key considerations in our topology selection and refinement include:

• Power factor correction and harmonic filtering
• Dynamic response vs. EMI tradeoffs
• Converter stability under varying loads
• Partial-load and peak-efficiency optimization
   

We regularly support multi-output converters, auxiliary rails, startup sequencing, and load-sharing mechanisms for high-reliability systems.

We design and implement full custom VFD solutions, including:

• Input stage design: AC mains, DC bus, and active/passive PFC
• Output inverter stage: 3-phase, multi-phase, or single-phase motor outputs
• Control loop tuning: for torque, speed, and vector control modes
• Auxiliary systems: fan drive outputs, braking circuits, regenerative stages, and EMI-compliant switching
   

Drives are architected to meet system-level goals:

• Low acoustic noise, high torque density, and adaptive speed control
• Configurable soft-start, fault shutdown, and inrush protection
• Support for induction, PMAC, and hybrid motors
• Optimized for manufacturing, field upgradeability, and thermal margin

A dedicated loop ensures device, package, and driver act as one.

• Devices: SiC, GaN, IGBT, super‑junction (SJ) MOSFETs
• Packages: ACEPACK, EasyPACK, DIPIPM, CIPOS, TO‑220/247, IPM, PIM
   

Gate‑drive features

• Desaturation detection with programmable blanking
• Programmable di/dt and dv/dt shaping for soft turn‑on/off
• Active Miller clamp and multi‑level drive for SiC devices
• Galvanic isolation via optical, capacitive, or transformer methods
   

Simulation & validation

• Overshoot, ringing, and parasitic‑loop extraction
• Short‑circuit SOA verification and shut‑down timing
• Die‑temperature mapping under worst‑case duty
• Gate‑driver timing overlap vs. thermal stack integrity

Modulation strategy is chosen to maximize system efficiency and EMI margin.

• Space‑Vector PWM (SVPWM) & Bus‑Clamped SVM (BC‑SVM) for harmonic reduction
• Six‑step & over‑modulation for high‑speed or minimal‑resource drives
• Table‑based space‑vector lookup for deterministic fixed‑point controllers
• Hysteretic and peak‑mode control for torque‑dense applications
• Combined modulation‑and‑tank approaches that preserve ZVS across load range
   

Algorithm optimizations:

• Thermal margin via real‑time MTPA
• Noise shaping through phase interleaving
• Grid‑coupled power‑factor correction

EMI compliance is designed‑in from day one.

We provide:

• Common‑mode and differential‑mode filter synthesis
• Layout strategies that minimize parasitic coupling
• Shielding, grounding, and cable management guidance
• Compliance with CISPR 32, CISPR 25, EN 61000‑6‑4/‑2, SAE J1113‑2/‑4, FCC Part 15
   

Our process:

• EMI modeling at schematic and PCB level
• Modulation noise simulation and spectrum prediction
• Filter prototyping and parasitic tuning
• Pre‑compliance scans and formal test support

A unified toolchain drives first‑pass success.

• Simulation: PSIM, LTspice, PLECS, MATLAB/Simulink
• PCB & layout: Cadence Allegro, OrCAD, Altium
• EMI/EMC: Ansys EMA3D, SiWave
• Thermal & mechanical: ANSYS Icepak, Flotherm
• Loss & gate‑drive: Sigrity PowerSI / PowerDC, SmartCtrl
   

We execute:

• Switching‑loss and SOA analysis
• Worst‑case thermal & EMI validation
• Inrush / shutdown transition profiles
• EMI test planning with waveform capture